Dynamic integrated circuit memories such as a dynamic random access memory (DRAM) traditionally store data as a charge on a memory cell capacitor. For example, a logical "one" is stored as positive charge on the capacitor and a logical "zero" is stored as negative charge on the capacitor. Because of the dense population of memory cells in an integrated circuit, the capacitance of each memory cell is small and the available charge is proportionally small. To read data from the memory cells, therefore, the charge must be sensed and amplified.
Typical memory circuits are designed to have pairs of data lines selectively coupled to the memory cells. The data line pairs are pre-charged to an equal potential between ground and the supply potential. When a memory cell is coupled to one of the data lines, a differential voltage is established between the data line pairs. An n-channel sense amplifier is used to detect the differential voltage and pull the low data line to ground. Likewise, a p-channel sense amplifier is used to detect the differential and drive the high data line to the supply voltage.
As stated, the DRAM memory cell is dynamic, and as such the data must be periodically refreshed by writing back the data to the memory cell. To extend the period between write backs, the initial charge stored on the memory cell should be provided using the maximum available potential voltage. To maintain a maximum charging potential during the memory cell refresh, the p-sense amplifiers may be coupled directly to the memory cell, or by using an isolation device, such as a transistor having a pumped gate voltage. Additional current must, therefore, be provided to source the pumped gate voltage.
Driver circuits for driving devices such as the isolation device which requires a pumped gate voltage have typically pulled all the charge necessary to drive the load from a pumped or elevated voltage source. Such drivers require an undesired level of current needed to drive the isolation devices entirely from the pumped voltage source.
In addition, conventional output driver circuits utilize complementary metal-on-semiconductor (CMOS) technology. A conventional CMOS output circuit includes a p-channel MOS (PMOS) transistor coupled between voltage and an output node, and an n-channel MOS (NMOS) transistor coupled between the output node and ground. The CMOS design enables the PMOS transistor to be "on" while the NMOS transistor is "off", and vice versa, in response to a single input signal. When the PMOS transistor is "on" and the NMOS transistor is "off", the CMOS driver circuit outputs a voltage. Conversely, when the PMOS transistor is "off" and the NMOS transistor is "on", the output of the CMOS driver circuit is grounded.
A drawback inherent in the design of conventional CMOS output driver circuits is that during the low to high voltage swing at the input to the device, there exists a period of time when both the PMOS and NMOS transistors are "on." This dual activation condition causes a phenomenon known as "crossing current" which wastes power.
Therefore, there is a need in the art for a driver circuit that reduces the level of charge pulled from the pumped or elevated voltage source. In addition, the driver circuit should eliminate or substantially reduce crossing current in an effort to conserve power.